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data sheet ics840n202cki revision a november 1, 2013 1 ?2013 integrated device technology, inc. femtoclock? ng universal frequency translator ICS840N202I general description the ICS840N202I is a highly flexible femtoclock? ng general purpose, low phase noise frequency translator / synthesizer with alarm and monitoring functions suitable for networking and communications applications. it is able to generate any output frequency in the 1mhz - 250mhz range (see table 3 for details). a wide range of input reference clocks and a range of low-cost fundamental mode crystal frequencies may be used as the source for the output frequency. the ICS840N202I has three operating modes to support a very broad spectrum of applications: 1) frequency synthesizer ? synthesizes output frequencie s from a 16mhz - 40mhz fundamental mode crystal. ? fractional feedback division is used, so there are no requirements for any specific crystal frequency to produce the desired output frequency with a high degree of accuracy. 2) high-bandwidth frequency translator ? applications: pci express, computing, general purpose ? translates any input clock in the 16mhz - 710mhz frequency range into any supported output frequency. ? this mode has a high pll loop bandwidth in order to track input reference changes, such as spread-spectrum clock modulation, so it will not attenuate much jitter on the input reference. 3) low-bandwidth frequency translator ? applications: networking & communications. ? translates any input clock in the 8khz - 710mhz frequency range into any supported output frequency. ? this mode supports pll loop bandwidths in the 10hz - 580hz range and makes use of an external crystal to provide significant jitter attenuation. this device provides two factory-programmed default power-up configurations burned into one-time programmable (otp) memory. the configuration to be used is se lected by the config pin. the two configurations are specified by th e customer and are programmed by idt during the final test phase from an on-hand stock of blank devices. the two configurations may be completely independent of one another. one usage example might be to install the device on a line card with two optional daughter cards: an oc-3 option (configuration 0) requiring a 155.52mhz clock trans lated from a 19.44mhz input and a gigabit ethernet option (configurat ion 1) requiring a 125mhz clock translated from the same 19.44mhz input reference. to implement other configurations , these power-up default settings can be overwritten after power-up using the i 2 c interface and the device can be completely reconfigured. however, these settings would have to be re-written each time the device powers-up. features ? fourth generation femtoclock? ng technology ? universal frequency translator/frequency synthesizer ? two lvcmos/lvttl outputs ? both outputs may be set to use 2.5v or 3.3v output levels ? programmable output frequency: 1.0mhz to 250mhz ? two differential inputs support the following input types: lvpecl, lvds, lvhstl, hcsl ? input frequency range: 8khz - 710mhz ? crystal input frequency range: 16mhz - 40mhz ? two factory-set register configurations for power-up default state ? power-up default configurati on pin or register selectable ? configurations customized via one-time programmable rom ? settings may be overwritten after power-up via i 2 c ? i 2 c serial interface for register programming ? rms phase jitter at 125mhz, using a 40mhz crystal (12khz - 20mhz): 616fs (typical), low bandwidth mode (fracn) ? output supply voltage modes: v dd /v dda /v ddo 3.3v/3.3v/3.3v 3.3v/3.3v/2.5v 2.5v/2.5v/2.5v ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) packaging pin assignment 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 xtal_in xtal_out v dd clk_sel clk0 nclk0 v dd gnd clk1 nclk1 lock_ind v dd gnd oe0 gnd q0 v ddo q1 gnd oe1 nc pll_bypass v dd sdata sclk config s_a1 s_a0 rsvd rsvd xtalbad clk1bad v dda gnd lf1 lf0 clk_active nc holdover clk0bad ICS840N202I 40 lead vfqfn 6mm x 6mm x 0.925mm k package top view
ics840n202cki revision a november 1, 2013 2 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator complete block diagram pd/lf n[10:0] m_int [7:0] m_frac [17:0] m1[16:0] pd/cp p[16:0] adc c s output divider q0 q1 cl k0 cl k1 cl k_se l pll_bypass lock_ind clk0bad clk1bad clk_active xtalbad oe0 oe1 osc xtal_in xtal_out register set 0 register set 1 global regist ers control logic otp sclk, s_a0, s_a1 sdata por config femtoclock ? ng vco 1995 - 2600 mhz holdover status indicators xtal feedback divider r s c p lf1 4 r 3 lf0 c 3 nclk1 nclk0 0 1 1 0 1 0
ics840n202cki revision a november 1, 2013 3 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator pin description and pin characteristic tables table 1. pin descriptions number name type description 1 2 xtal_in xtal_out input crystal oscillator interface designed fo r 12pf parallel resonant crystals. xtal_in (pin 1) is the input and xtal_out (pin 2) is the output. 3, 7, 13, 29 v dd power core supply pins. all must be either 3.3v or 2.5v. 4 clk_sel input pulldown input clock select. selects the active differential clock input. 0 = clk0, nclk0 (default) 1 = clk1, nclk1 5 clk0 input pulldown non-inverting differential clock input. 6 nclk0 input pullup/ pulldown inverting differenti al clock input. v dd /2 default when left floating (set by the internal pullup and pulldown resistors). 8, 21, 23, 27, 35 gnd power power supply pins. 9 clk1 input pulldown non-inverting differential clock input. 10 nclk1 input pullup/ pulldown inverting differenti al clock input. v dd /2 default when left floating (set by the internal pullup and pulldown resistors). 11, 32 nc unused no connect. these pins are to be left unconnected. 12 pll_bypass input pulldown bypasses the vcxo pll. 0 = pll not bypassed (default) 1 = pll bypassed 14 sdata i/o pullup i 2 c data input/output. open drain. lvcmos/lvttl interface levels. 15 sclk input pullup i 2 c clock input. lvcmos/lvttl interface levels. 16 config input pulldown configuration pin. selects between one of two factory programmable pre-set power-up default configurations. the tw o configurations can have different output/input frequency translation rati os, different pll loop bandwidths, etc. these default configurations can be overwritten after power-up via i 2 c if the user so desires. 0 = configuration 0 (default) 1 = configuration 1 17 s_a1 input pulldown i 2 c address bit 1. lvcmos/lvttl interface levels. 18 s_a0 input pulldown i 2 c address bit 0. lvcmos/lvttl interface levels. 19, 20 rsvd reserved reserved for future use. should be left unconnected. 22 oe1 input pullup active high output enable for q1. 0 = output pins high-impedance 1 = output switching (default) 24 q1 output clock output. lvcmos/lvttl interface levels. 25 v ddo power output supply voltage. either 2.5v or 3.3v. 26 q0 output clock output. lvcmos/lvttl interface levels. 28 oe0 input pullup active high output enable for q0. 0 = output pins high-impedance 1 = output switching (default) 30 lock_ind output lock indicator - indicates that the pll is in a locked condition. lvcmos/lvttl interface levels. 31 clk_active output indicates which of the two differentia l clock inputs is currently selected. 0 - clk0, nclk0 differential input pair 1 - clk1, nclk1 differential input pair
ics840n202cki revision a november 1, 2013 4 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics 33, 34 lf0, lf1 input loop filter connection node pins. lf0 is the output. lf1 is the input. 36 v dda power analog supply voltage. see applications section for details on how to connect this pin. 37 holdover output alarm output reflecting if the device is in a holdover state. lvcmos/lvttl interface levels. 0 = device is locked to a valid input reference 1 = device is not locked to a valid input reference 38 clk0bad output alarm output reflecting the state of clk0. lvcmos/lvttl interface levels. 0 = input clock 0 is switching within specifications 1 = input clock 0 is out of specification 39 clk1bad output alarm output reflecting the state of clk1. lvcmos/lvttl interface levels. 0 = input clock 1 is switching within specifications 1 = input clock 1 is out of specification 40 xtalbad output alarm output reflecting the state of xtal. lvcmos/lvttl interface levels. 0 = crystal is switching within specifications 1 = crystal is out of specification symbol parameter test conditio ns minimum typical maximum units c in input capacitance xtal_in, xtal_out, pll_bypass, config, a0, a1, oe0, oe1, sclk 4p f c pd power dissipation capacitance 8 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance q0, q1 15 ? clk_active, holdover, xtalbad, clk0bad, clk1bad, lock_ind 25 ?
ics840n202cki revision a november 1, 2013 5 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator functional description the ICS840N202I is designed to provide two copies of almost any desired output frequency within its operating range (0.98 - 250mhz) from any input source in the operating range (8khz - 710mhz). it is capable of synthesizing frequencies from a crystal or crystal oscillator source. the output frequency is generated regardless of the relationship to the input frequency. the output frequency will be exactly the required frequency in most cases. in most others, it will only differ from the desired frequency by a few ppb. idt configuration software will indicate the frequency error, if any. the ICS840N202I can translate the desired output frequency from one of two input clocks. again, no relationship is required between the input and output frequencies in order to translate to the output clock rate. in this frequency translation mode, a low-bandwidth, jitter attenuation option is available that makes use of an external fixed-frequency crystal or crystal oscillator to translate from a noisy input source. if the input clock is known to be fairly clean or if some modulation on the input needs to be tracked, then the high-bandwidth frequency translation mode can be used, without the need for the external crystal. the input clock references and crystal input are monitored continuously and appropriate al arm outputs are raised both as register bits and hard-wired pins in the event of any out-of-specification conditions arisin g. clock switching is supported in manual, revertive & non-revertive modes. the ICS840N202I has two factory- programmed configurations that may be chosen from as the default op erating state after reset. this is intended to allow the same device to be used in two different applications without any need for access to the i 2 c registers. these defaults may be over-written by i 2 c register access at any time, but those over-written settings will be lost on power-down. please contact idt if a specific set of power-up default settings is desired. configuration selection the ICS840N202I comes with two factory-programmed default configurations. when the device comes out of power-up reset the selected configuration is loaded into operating registers. the ICS840N202I uses the state of th e config pin or config register bit (controlled by the cfg_pin_reg bit) to determine which configuration is active. when the ou tput frequency is changed either via the config pin or via internal registers, the output behavior may not be predictable during the regi ster writing and output settling periods. devices sensitive to glitches or runt pulses may have to be reset once reconfiguration is complete. once the device is out of reset, th e contents of the operating registers can be modified by write access from the i 2 c serial port. users that have a custom configuration programmed may not require i 2 c access. it is expected that the ICS840N202I will be used almost exclusively in a mode where the selected confi guration will be used from device power-up without any changes during operation. for example, the device may be designed into a communications line card that supports different i/o modules such as a standard oc-3 module running at 155.52mhz or a (255/23 7) fec rate oc-3 module running at 167.332mhz. the different i/o modu les would result in a different level on the config pin which would select different divider ratios within the ICS840N202I for the two different card configurations. access via i 2 c would not be necessary for operation using either of the internal configurations. operating modes the ICS840N202I has three operating modes which are set by the mode_sel[1:0] bits. there are two frequency translator modes - low bandwidth and high bandwidth and a frequency synthesizer mode. the device will operate in the same mode regardless of which configuration is active. please make use of idt-provided configuration applications to determine the best operating settings for the desired configurations of the device. output dividers & supported output frequencies in all 3 operating modes, the output stage behaves the same way, but different operating frequencies can be specified in the two configurations. the internal vco is capable of operating in a range anywhere from 1.995ghz - 2.6ghz. it is necessary to choose an integer multiplier of the desired output frequency that results in a vco operating frequency within that range. th e output divider stage n[10:0] is limited to selection of even integers from 10 to 2046. please refer to table 3 for the values of n applicable to the desired output frequency. table 3. output divider settings & frequency ranges note 1: using a divider setting of n = 0x00a or 0x00b with a high vco frequency can result in the cmos output running faster than its 250mhz maximum operating frequency. frequency synthesizer mode this mode of operation allows an arbitrary output frequency to be generated from a fundamental m ode crystal input. as can be seen from the block diagram in figure 1, only the upper feedback loop is used in this mode of operation. register setting frequency divider minimum f out maximum f out nn[10:0] n (mhz) (mhz) 00000000000 - 0000000100x 2 - 8 not supported 0000000101x 10 199.5 260 (note 1) 0000000110x 12 166.3 216.7 0000000111x 14 142.5 185.7 0000001000x 16 124.7 162.5 0000001001x 18 110.8 144.4 ... even n 1995 / n 2600 / n 1111111111x 2046 0.98 1.27
ics840n202cki revision a november 1, 2013 6 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator the upper feedback loop supports a delta-sigma fractional feedback divider. this allows the vco operating frequency to be a non-integer multiple of the crystal frequency. by using an integer multiple only, lower phase noise jitter on the output can be achieved, however the use of the delta-sigma divider logic will provide excellent performance on the output if a fractional divisor is used. figure 1. frequency synthesizer mode block diagram high-bandwidth frequency translator mode this mode of operation is used to translate one of two input clocks of the same nominal frequency into an output frequency with little jitter attenuation. as can be seen from the block diagram in figure 2, similarly to the frequency synthesizer mode, only the upper feedback loop is used. figure 2. high bandwidth frequency translator mode block diagram the input reference frequency range is now extended up to 710mhz. a pre-divider stage p is needed to keep the operating frequencies at the phase detector within limits. low-bandwidth frequency translator mode as can seen from the block diagram in figure 3, this mode involves two pll loops. the lower loop with the large integer dividers is the low bandwidth loop and it sets the output-to-input frequency translation ratio.this loop drives the upper dcxo loop (digitally controlled crystal oscillator) via an analog-digital converter. figure 3. low bandwidth frequency translator mode block diagram the phase detector of the lower loop is designed to work with frequencies in the 8khz - 16khz range. the pre-divider stage is used to scale down the input frequency by an integer value to achieve a frequency in this range. by dividing down the fed-back vco operating frequency by the integer divider m1[18:0] to as close as possible to the same frequency, very accurate output frequency translations can be achieved. alarm conditio ns & status bits the ICS840N202I monitors a number of conditions and reports their status via both output pins and register bits. all alarms will behave as indicated below in all modes of operation, but some of the conditions monitored have no valid meaning in some operating modes. for example, the status of clk0bad, clk1bad and clk_active are not relevant in frequency synthesizer mode. the outputs will still be active and it is left to the user to determine which to monitor and how to respond to them based on the known operating mode. clk_active - indicates which input clock reference is being used to derive the output frequency. lock_ind - this status is asserted on the pin & register bit when the pll is locked to the appropriate input reference for the chosen mode of operation. the status bit will not assert until frequency lock has been achieved, but will de-assert once lock is lost. xtalbad - indicates if valid edges are being received on the crystal input. detection is performed by comparing the input to the feedback signal at the upper loop?s phase / frequency detector (pfd). if three edges are received on the feedback without an edge on the crystal input, the xtalbad alarm is asserted on the pin & register bit. once an edge is detected on the crystal input, the alarm is immediately deasserted. pd/lf n[10:0] m_in t [7:0] m_frac [17:0] m1[16:0] pd/cp p[16:0] adc c s output divider q0 q1 cl k0 cl k1 cl k_se l pll_bypass lo ck_ind clk0bad clk1bad clk_active xtalbad oe0 oe1 osc xtal_in xtal_out register set 0 register set 1 global registers control logic otp sclk, s_a0, s_a1 sdata por config femtoclock? ng vco 1995 - 2600 mhz holdover status indicators xtal feedback divider r s c p lf1 4 r 3 lf0 c 3 nclk1 nclk0 0 1 1 0 1 0
ics840n202cki revision a november 1, 2013 7 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator clk0bad - indicates if valid edges are being received on the clk0 reference input. detection is performed by comparing the input to the feedback signal at the appropriate phase / frequency detector (pfd). when operating in high-bandwidth mode, the feedback at the upper pfd is used. in low-bandwidth mode, the feedback at the lower pfd is used. if three edges are received on the feedback without an edge on the divided down (p) clk0 reference input, the clk0bad alarm is asserted on the pin & register bit. once an edge is detected on the clk0 reference input, the alarm is deasserted. clk1bad - indicates if valid edges are being received on the clk1 reference input. behavior is as indicated for the clk0bad alarm, but with the clk1 input being monito red and the clk1bad output pin & register bits being affected. holdover - indicates that the device is not locked to a valid input reference clock. this can occur in manual switchover mode if the selected reference input has gone bad, even if the other reference input is still good. in automatic mode, this will only assert if both input references are bad. input reference select ion and switching when operating in frequency synthesizer mode, the clk0 and clk1 inputs are not used and the contents of this section do not apply. except as noted below, when operating in either high or low bandwidth frequency translator mode, the contents of this section apply equally when in either of those modes. both input references clk0 and clk1 must be the same nominal frequency. these may be driven by any type of clock source, including crystal oscillator modules. a difference in frequency may cause the pll to lose lock when switching between input references. please contact idt for the exact limits for your situation. the global control bits auto_man[1 :0] dictate the order of priority and switching mode to be used between the clk0 and clk1 inputs. manual switching mode when the auto_man[1:0] field is set to manual via pin, then the ICS840N202I will use the clk_sel input pin to determine which input to use as a reference. similarly, if set to manual via register, then the device will use the clk_sel register bit to determine the input reference. in either case, the pll will lock to the selected reference if there is a valid clock present on that input. if there is not a valid clock present on the selected input, the ICS840N202I will go into holdover (low bandwidth frequency translator mode) or free-run (high bandwidth frequency translator mode) state. in either case, the holdover alarm will be raised. this will occur even if there is a valid clock on the non-selected reference input. the device will recover from holdover / free-run state once a valid clock is re-established on the selected reference input. the ICS840N202I will only switch input references on command from the user. the user must either change the clk_sel register bit (if in manual via register) or clk_sel input pin (if in manual via pin). automatic switching mode when the auto_man[1:0] field is set to either of the automatic selection modes (revertive or non-revertive), the ICS840N202I determines which input reference it prefers / starts from by the state of the clk_sel register bit only. the clk_sel input pin is not used in either automatic switching mode. when starting from an unlocked condit ion, the device will lock to the input reference indicated by the clk_sel register bit. it will not pay attention to the non-selected input reference until a locked state has been achieved. this is necessary to prevent ?hunting? behavior during the locking phase. once the ICS840N202I has achieved a stable lock, it will remain locked to the preferred input reference as long as there is a valid clock on it. if at some point, that clock fails, then the device will automatically switch to the other input reference as long as there is a valid clock there. if there is not a valid clock on either input reference, the ICS840N202I will go into holdover (low bandwidth frequency translator mode) or free-run (high bandwidth frequency translator mode) state. in either case, the holdover alarm will be raised. the device will recover from holdover / free-run state once a valid clock is re-established on either reference input. if clocks are valid on both input references, the device will choose the reference indicated by the clk_sel register bit. if running from the non-preferred input reference and a valid clock returns, there is a difference in behavior between revertive and non-revertive modes. in revertive mode, the device will switch back to the reference indicated by the clk_sel register bit even if there is still a valid clock on the non-preferred reference input. in non-revertive mode, the ICS840N202I will not switch back as long as the non-preferred input reference still has a valid clock on it. switchover behavior of the pll even though the two input references have the same nominal frequency, there may be minor differences in frequency and potentially large differences in phase between them. the ICS840N202I will adjust its output to the new input reference. it will use phase slope limiting to adjust the output phase at a fixed maximum rate until the output phase and frequency are now aligned to the new input reference. phase will always be adjusted by extending the clock period of the output so that no unacceptably short clock periods are generated on the output ICS840N202I. holdover / free-run behavior when both input references have failed (automatic mode) or the selected input has failed (manual mode), the ICS840N202I will enter holdover (low bandwidth frequency translator mode) or free-run (high bandwidth frequency translator mode) state . in both cases, once both input references are lost, the pll will stop making adjustments to the output phase. if operating in low bandwidth frequency translation mode, the pll will continue to reference itself to the local oscillator and will hold its output phase and frequency in relation to that source. output stability is determined by the stability of the local oscillator in this case.
ics840n202cki revision a november 1, 2013 8 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator however, if operating in high bandwidth frequency translation mode, the pll no longer has any frequency reference to use and output stability is now determined by the stability of the internal vco. if the device is programmed to perform manual switching, once the selected input reference recovers, the ICS840N202I will switch back to that input reference. if programmed for either automatic mode, the device will switch back to whichever input reference has a valid clock first. the switchover that results from re turning from holdover or free-run is handled in the same way as a switch between two valid input references as described in the previous section. output configuration the two outputs of the ICS840N202I both provide the same clock frequency. both must operate from the same output voltage level of 3.3v or 2.5v, although this output voltage may be less than or equal to the core voltage (3.3v or 2.5v) the rest of the device is operating from. the output voltage level used on the two outputs is supplied on the v ddo pin. the two outputs can be enabled individually via both register control bits and input pins. when both t he oen register bit and oen pin are enabled, then the appropriate output is enabled. the oen register bits default to enabled so that by default the outputs can be directly controlled by the input pins. similarly, the input pins are provisioned with weak pull-ups so that if they are left unconnected, the output state can be directly controlled by the register bits. when the output is in the disabled state, it will show a high impedance condition. serial interface configuration description the ICS840N202I has an i 2 c-compatible configuration interface to access any of the internal registers (table 4d) for frequency and pll parameter programming. the ICS840N202I acts as a slave device on the i 2 c bus and has the address 0b11011xx, where xx is set by the values on the s_a0 & s_a1 pins (see table 4a for details). the interface accepts byte-oriented block write and block read operations. an address byte (p) specifies the register address (table 4d) as the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first, see table 4b, 4c). read and write block transfers can be stopped after any complete byte transfer. it is recommended to terminate i 2 c the read or write transfer after accessing byte #23. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 50k ? typical. note: if a different device slave address is desired, please contact idt. table 4a. i 2 c device slave address table 4b. block write operation table 4c. block read operation 11011s_a1s_a0r/w bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ... description start slave address w (0) ack address byte (p) ack data byte (p) ack data byte (p+1) ack data byte ... ack stop length (bits) 1711818181811 bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ... description start slave address w (0) a c k address byte (p) a c k repeated start slave address r (1) a c k data byte (p) a c k data byte (p+1) a c k data byte ... a c k stop length (bits 1711811 7118181811
ics840n202cki revision a november 1, 2013 9 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator register descriptions please consult idt for configuration software and/or progra mming guides to assist in sele ction of optimal register settings for the desired configurations. table 4d. i 2 c register map register bit color key regi ster binary register address register bit d7 d6 d5 d4 d3 d2 d1 d0 0 00000 mfrac0[17] mfrac0[16] mfrac0[15] mfrac0[14] mfrac0[13] mfrac0[12] mfrac0[11] mfrac0[10] 1 00001 mfrac1[17] mfrac1[16] mfrac1[15] mfrac1[14] mfrac1[13] mfrac1[12] mfrac1[11] mfrac1[10] 2 00010 mfrac0[9] mfrac0[8] mfrac0[7] mfrac0[6] mfrac0[5] mfrac0[4] mfrac0[3] mfrac0[2] 3 00011 mfrac1[9] mfrac1[8] mfrac1[7] mfrac1[6] mfrac1[5] mfrac1[4] mfrac1[3] mfrac1[2] 4 00100 mfrac0[1] mfrac0[0] mint0[7] mint0[6] mint0[5] mint0[4] mint0[3] mint0[2] 5 00101 mfrac1[1] mfrac1[0] mint1[7] mint1[6] mint1[5] mint1[4] mint1[3] mint1[2] 6 00110 mint0[1] mint0[0] p0[16] p0[15] p0[14] p0[13] p0[12] p0[11] 7 00111 mint1[1] mint1[0] p1[16] p1[15] p1[14] p1[13] p1[12] p1[11] 8 01000 p0[10] p0[9] p0[8] p0[7] p0[6] p0[5] p0[4] p0[3] 9 01001 p1[10] p1[9] p1[8] p1[7] p1[6] p1[5] p1[4] p1[3] 10 01010 p0[2] p0[1] p0[0] m1_0[16] m1_0[15] m1_0[14] m1_0[13] m1_0[12] 11 01011 p1[2] p1[1] p1[0] m1_1[16] m1_1[15] m1_1[14] m1_1[13] m1_1[12] 12 01100 m1_0[11] m1_0[10] m1_0[9] m1_0[8] m1_0[7] m1_0[6] m1_0[5] m1_0[4] 13 01101 m1_1[11] m1_1[10] m1_1[9] m1_1[8] m1_1[7] m1_1[6] m1_1[5] m1_1[4] 14 01110 m1_0[3] m1_0[2] m1_0[1] m1_0[0] n0[10] n0[9] n0[8] n0[7] 15 01111 m1_1[3] m1_1[2] m1_1[1] m1_1[0] n1[10] n1[9] n1[8] n1[7] 16 10000 n0[6] n0[5] n0[4] n0[3] n0[2] n0[1] n0[0] bw0[6] 17 10001 n1[6] n1[5] n1[4] n1[3] n1[2] n1[1] n1[0] bw1[6] 18 10010 bw0[5] bw0[4] bw0[3] bw0[2] bw0[1] bw0[0] rsvd rsvd 19 10011 bw1[5] bw1[4] bw1[3] bw1[2] bw1[1] bw1[0] rsvd rsvd 20 10100 mode_sel[1] mode_sel[0] config cfg_pin_reg oe1 oe0 rsvd rsvd 21 10101 clk_sel auto_man[1] auto_man[0] 0 adc_rate[1] adc_rate[0] lck_win[1] lck_win[0] 22 10110 1 0 1 0 0 0 0 0 23 10111 clk_active holdover clk1bad clk0bad xtal_bad lock_ind rsvd rsvd configuration 0 specific bits configuration 1 specific bits global control & status bits
ics840n202cki revision a november 1, 2013 10 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator the register bits described in table 4e are duplicated, with one set applying for configuration 0 and th e other for configuration 1. the functions of the bits are identical, but only apply when the configuration they apply to is enabled. replace the lowercase n in the bit field description with 0 or 1 to find the field?s location in the bitmap in table 4d. table 4e. configuration-specific control bits table 4f. global control bits register bits function pn[16:0] reference pre-divider for configuration n. m1_n[16:0] integer feedback divider in lower feedback loop for configuration n. m_intn[7:0] feedback divider, integer value in upper feedback loop for configuration n. m_fracn[17:0] feedback divider, fractional value in upper feedback loop for configuration n. nn[10:0] output divider for configuration n. bwn[6:0] internal operation settings for configuration n. please use idt ICS840N202I configuration software to determ ine the correct settings for these bits for the specific configuration. alternatively, please consult with idt directly for further in formation on the functions of these bits.the function of these bits is explained in tables 4j and 4k. register bits function mode_sel[1:0] pll mode select 00 = low bandwidth frequency translator 01 = frequency synthesizer 10 = high bandwidth frequency translator 11 = high bandwidth frequency translator cfg_pin_reg configuration control. select s whether the configuration selection function is under pin or register control. 0 = pin control 1 = register control config configuration selection. selects whether the device uses t he register configuration set 0 or 1. this bit only has an effect when the cfg_pin_reg bit is set to 1 to enable register control. oe0 output enable control for output 0. both this register bit and the corresponding output enable pin oe0 must be asserted to enable the q0 output. 0 = output q0 disabled 1 = output q0 under control of the oe0 pin oe1 output enable control for output 1. both this register bit and the corresponding output enable pin oe1 must be asserted to enable the q1 output. 0 = output q1 disabled 1 = output q1 under control of the oe1 pin rsvd reserved bits - user should write a ?0? to these bit positions if a write to these registers is needed auto_man[1:0] selects how input clock selection is performed. 00 = manual selection via pin only 01 = automatic, non-revertive 10 = automatic, revertive 11 = manual selection via register only clk_sel in manual clock selection via register mode, this bit w ill command which input clock is selected. in the automatic modes, this indicates the primary clock input. in manual selection via pin mode, this bit has no effect. 0 = clk0 1 = clk1 adc_rate[1:0] sets the adc sampling rate in low-bandwidth mo de as a fraction of the crystal input frequency. 00 = crystal frequency / 16 01 = crystal frequency / 8 10 = crystal frequency / 4 (recommended) 11 = crystal frequency / 2 lck_win[1:0] sets the width of the window in which a new reference ed ge must fall relative to the feedback edge: 00 = 2usec (recommended), 01 = 4usec, 10 = 8usec, 11 = 16usec
ics840n202cki revision a november 1, 2013 11 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator table 4g. global status bits table 4j. bw[6:0] bits register bits function clk0bad status bit for input clock 0. this function is mirrored in the clk0bad pin. 0 = input clk0 is good 1 = input clk0 is bad. self clears when input clock returns to good status clk1bad status bit for input clock 1. this function is mirrored in the clk1bad pin. 0 = input clk1 is good 1 = input clk1 is bad. self clears when input clock returns to good status xtalbad status bit. this function is mirrored on the xtalbad pin. 0 = crystal input good 1 = crystal input bad. self-clears when the xtal clock returns to good status lock_ind status bit. this function is mirrored on the lock_ind pin. 0 = pll unlocked 1 = pll locked holdover status bit. this function is mirrored on the holdover pin. 0 = input to phase detector is within specifications and device is tracking to it 1 = phase detector input not wit hin specifications and dcxo is frozen at last value clk_active status bit. indicates which input clock is active. automatically updates during fail-over switching. status also indicated on clk_active pin. mode bw[6] bw[5] bw[4] b w[3] bw[2] bw[1] bw[0] synthesizer mode pll2_lf[1] pll2_lf[0] dsm_ord dsm_en pll2_cp[1] pll2_cp[0] pll2_low_icp high-bandwidth mode pll2_lf[1] pll2_lf[0] dsm_ord dsm_en pll2_cp[1] pll2_cp[0] pll2_low_icp low-bandwidth mode adc_gain[3] adc_gain[2] adc_gain[1] adc_gain[0] pll1_cp[1] pll1_cp[0] pll2_low_icp
ics840n202cki revision a november 1, 2013 12 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator table 4k. functions of fields in bw[6:0] table 4l. upper loop (pll2) bandwidth settings note: to achieve 4mhz bandwidth, reference to the phase detector should be 80mhz. register bits function pll2_lf[1:0] sets loop filter values for upper loop pll in frequency synthesizer & high-bandwidth modes. defaults to setting of 00 when in low bandwidth mode. see table 4l for settings. dsm_ord sets delta-sigma modulation to 2nd (0) or 3rd order (1) operation. dsm_en enables delta-sigma modulator. 0 = disabled - feedback in integer mode only 1 = enabled - feedback in fractional mode pll2_cp[1:0] upper loop pll charge pump current settings: 00 = 173 ? a (defaults to this setting in low bandwidth mode) 01 = 346 ? a 10 = 692 ? a 11 = reserved pll2_low_icp reduces charge pump current by 1/3 rd to reduce bandwidth variations resulting from higher feedback register settings or high vco operating frequency (>2.4ghz). adc_gain[3:0] gain setting for adc in low bandwidth mode. pll1_cp[1:0] lower loop pll charge pump current settings (lower loop is only used in low bandwidth mode): 00 = 800 ? a 01 = 400 ? a 10 = 200 ? a 11 = 100 ? a desired bandwidth pll2_cp pll2icp pll2_lf frequency synthesizer mode 200khz 00 1 00 400khz 01 1 01 800khz 10 1 10 2mhz 10 1 11 high bandwidth frequency translator mode 200khz 00 1 00 400khz 01 1 01 800khz 10 1 10 4mhz 10 0 11 low bandwidth frequency translator mode 200khz 00 00
ics840n202cki revision a november 1, 2013 13 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 5a. power supply dc characteristics, v dd = v ddo = 3.3v5%, t a = -40c to 85c table 5b. power supply dc characteristics, v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c table 5c. power supply dc characteristics, v dd = v ddo = 2.5v5%, t a = -40c to 85c item rating supply voltage, v dd 3.63v inputs, v i xtal_in other input 0v to 2v -0.5v to v dd + 0.5v outputs, v o (lvcmos) -0.5v to v ddo + 0.5v outputs, sdata 10ma package thermal impedance, ? ja 32.4 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ?c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd + i ddo power + output supply current outputs unloaded 289 ma i dda analog supply current 31 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd + i ddo power + output supply current outputs unloaded 288 ma i dda analog supply current 31 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd + i ddo power + output supply current outputs unloaded 275 ma i dda analog supply current 29 ma
ics840n202cki revision a november 1, 2013 14 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator table 5d. lvcmos/lvttl dc characteristics, t a = -40c to 85c table 5e. differential dc characteristics, v dd = v ddo = 3.3v 5% or 2.5v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v . v ih should not be greater than v dd . note 2: common mode voltage is defined as the crosspoint. symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current clk_sel, config, pll_bypass, s_a[0:1] v dd = v in = 3.465v or 2.625v 150 a oe0, oe1, sclk, sdata v dd = v in = 3.465v or 2.625v 5 a i il input low current clk_sel, config, pll_bypass, s_a[0:1] v dd = 3.465v or 2.625v, v in = 0v -5 a oe0, oe1, sclk, sdata v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage xtalbad, clk0bad, clk1bad, clk_active, sdata, holdover, lock_ind v ddo = 3.465v, i oh = -8ma 2.6 v v ddo = 2.625v, i oh = -8ma 1.8 v q0, q1 v ddo = 3.465v, i oh = -12ma 2.6 v v ddo = 2.625v, i oh = -12ma 1.8 v v ol output low voltage xtalbad, clk0bad, clk1bad, clk_active, sdata, holdover, lock_ind v ddo = 3.465v or 2.625v, i oh = 8ma 0.5 v q0, q1 v ddo = 3.465v or 2.625v, i oh = 12ma 0.5 v symbol parameter test conditions minimum typical maximum units i ih input high current clk0, nclk0, clk1, nclk1 v dd = v in = 3.465v or 2.625v 150 a i il input low current clk0, clk1 v dd = 3.465v or 2.625v, v in = 0v -5 a nclk0, nclk1 v dd = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 1.0 v
ics840n202cki revision a november 1, 2013 15 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator table 6. input frequency characteristics, v dd = v ddo = 3.3v5% or 2.5v5%, or v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c note 1: for the input crystal and clkx, nclkx frequency range, the m value must be set for t he vco to operate within the 1995mh z to 2600mhz range. table 7. crystal characteristics symbol parameter test conditio ns minimum typical maximum units f in input frequency xtal_in, xtal_out note 1 16 40 mhz clk0, nclk0, clk1, nclk1 high bandwidth mode 16 710 mhz low bandwidth mode 0.008 710 mhz sclk 5mhz parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 16 40 mhz load capacitance (c l ) 12 pf equivalent series resistance (esr) 100 ? shunt capacitance 7pf
ics840n202cki revision a november 1, 2013 16 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator ac electrical characteristics table 8. ac characteristics, v dd = v ddo = 3.3v5% or 2.5v5%, or v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: above ac characteristics are measured with crystal c l = 12pf. note 1: rms phase jitter measured with crystal c l = 12pf. note 2: this parameter is defined in accordance with jedec standard 65. note 3: measurements are collected with the following output frequencies: 15mhz, 38 .88mhz, 50mhz, 68.88m hz, 125mhz, 132.61mhz, 156.25mhz, 161.1328125mhz, 200mhz, 233.33mhz, 250mhz. symbol parameter test conditions minimum typical maximum units f out output frequency 0.98 250 mhz t jit(?) rms phase jitter (random); note 1 lbw mode, 40mhz xtal, f in = 25mhz, f out = 125mhz, integration range: 12khz ? 20mhz 616 865 fs t jit(cc) cycle-to-cycle jitter; note 2, 3 frequency synthesizer mode 35 ps frequency translator mode 40 ps t jit(per) rms period jitter; note 3 1.4 4.5 ps t sk(o) output skew; note 2 50 ps t r / t f output rise/fall time; note 3 q0, q1 20% to 80% 100 750 ps odc output duty cycle: note 3 q0, q1 f out ? 125mhz 45 55 % q0, q1 125mhz < f out ? 200mhz 40 60 % q0, q1 f out > 200mhz 37 63 % t set output re-configuration settling time from falling edge of the 8th sclk for a register change 200 ns from edge on config pin 10 ns
ics840n202cki revision a november 1, 2013 17 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator typical phase noise at 125mhz (lbw mode) 125mhz rms phase jitter (random) 12khz to 20mhz = 616fs (typical) noise power dbc hz offset frequency (hz)
ics840n202cki revision a november 1, 2013 18 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator parameter measureme nt information 3.3 core/3.3v lvcmos output load test circuit 3.3 core/2.5v lvcmos output load test circuit differential input levels 2.5 core/2.5v lvcmos output load test circuit rms phase jitter output skew scope qx gnd v dda v dd, 1.65v+ 5% -1.65v5% v ddo 1.65v+ 5% blm18bb221sn1 scope qx gnd 2.05v+ 5% 1.25v+ 5% v dd -1.25v+ 5% v ddo v dda 2.05v+ 5% blm18bb221sn1 v dd gnd clkx nclkx scope qx gnd v dda v dd, 1.25v+ 5% -1.25v+ 5% v ddo 1.25v+ 5% blm18bb221sn1 qx qy t sk(o) v ddo 2 v ddo 2
ics840n202cki revision a november 1, 2013 19 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator parameter measurement in formation, continued single-ended output duty cycle/output pulse width/period cycle-to-cycle jitter single-ended output rise/fall time rms period jitter t period t pw t period odc = x 100% t pw q0, q1 ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles q0, q1 20% 80% 80% 20% t r t f q0, q1 v oh v ref v ol tjit(per) = (t per(n) ? t per mean) 2 / (n ? 1) t per(n) n = 1...10000 cycles 10000 n = 1
ics840n202cki revision a november 1, 2013 20 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator applications information recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. clkx/nclkx inputs for applications not requiring the use of either differential input, both clkx and nclkx can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clkx to ground. it is recommended that clkx, nclkx be left unconnected in frequency synthesizer mode. lvcmos control pins all control pins have internal pull-up or put-down resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs the unused lvcmos outputs can be left floating. there should be no trace attached. recommended values for low- bandwidth mode loop filter external loop filter components are not needed in frequency synthesizer or high-bandwidth modes. in low-bandwidth mode, the loop filter structure and components shown in figure 8 is recommended. please consult id t if other values are needed.
ics840n202cki revision a november 1, 2013 21 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator wiring the differential input to accept single-ended levels figure 4 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 4. recommended schematic for wiring a diff erential input to accept single-ended levels
ics840n202cki revision a november 1, 2013 22 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 5a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 5b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 5a. general diagram for lvcmos driver to xtal input interface figure 5b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
ics840n202cki revision a november 1, 2013 23 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator differential clock input interface the clk /nclk accepts lvds, l vpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 6a to 6e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 7a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 6a. clk/nclk input driven by an idt open emitter lvhstl driver figure 6c. clk/nclk input driven by a 3.3v lvpecl driver figure 6e. clk/nclk input driven by a 3.3v hcsl driver figure 6b. clk/nclk input driven by a 3.3v lvpecl driver figure 6d. clk/nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl differential in p u t h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50
ics840n202cki revision a november 1, 2013 24 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 7. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 7. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics840n202cki revision a november 1, 2013 25 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator schematic layout figure 8 (next page) shows an example of the ICS840N202I uft application schematic. input and output terminations shown are intended as examples only and may not represent the exact user configuration. in this exampl e, the device is operated at v dd = 3.3v. to use the 2.5v cmos output option, please refer to the section ?output configuration?. a 12pf par allel resonant 16mhz to 40mhz crystal is used in this example, though different crystal frequencies may be used. the load capacitance c1= 5pf and c2 = 5pf are recommended for frequency accuracy, but these may be adjusted for different board layouts. if different crystal types are used, please consult idt for recommendations. it is recommended that the loop f ilter components be laid out for the 3-pole option which can be adjusted for additional spur reduction and also allow for a 2-pole filter by setting r3 to 0 ohms and not populating c3. as with any high speed analog circuitry, the power supply pins are vulnerable to noise. to achieve optimum jitter performance, power supply isolation is required. the ICS840N202I uft provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the f ilter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pi n filter should be placed on the device side of the pcb and the ot her components can be placed on power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for wide range of noise frequencies. this low-pass filter starts to a ttenuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supply frequencies, it is re commended that component values be adjusted and if required, additi onal filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. the opposite side.
ics840n202cki revision a november 1, 2013 26 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator figure 8. ICS840N202I application schematic vd d c2 5pf c1 5pf set logic input to '0' set logic input to '1' to logic input pins lo gic i np ut pin ex am ple s to logi c input pins ru2 not in st alle d ru1 1k rd2 1k vd d rd1 no t in s t alle d vdd vd d c12 0.1uf c11 10 u f vddo c9 10uf c8 0.1uf c10 0.1uf 3. 3 v fb2 m ur at a , bl m1 8 bb22 1 sn 1 fb1 m ur at a , bl m1 8 bb22 1 sn 1 (note 2) (note 2) vdd uft u1 xt a l _ i n 1 xt a l _ o u t 2 clk_sel 4 clk0 5 clk0 6 clk1 9 clk1 10 pl l _b y pas s 12 s_ a0 18 s_ a1 17 sc l k 15 sd ata 14 conf ig 16 q0 26 oe0 28 q1 24 oe1 22 lock_ind 30 c l k_ a cti ve 31 ho l d o ve r 37 c l k0ba d 38 c l k1ba d 39 xtalba d 40 lf1 34 lf0 33 vddo 25 vd d 3 vd d 7 vd d 13 vdd 29 vdda 36 gn d 8 gnd 21 gnd 23 rsvd 19 rsvd 20 nc 11 nc 32 gnd 27 gnd 35 (note 1) (note 1) (note 1) (note 1) (note 1) rs 470k r3 220k cp 0.001uf lo ck _ind cs 1uf c3 0.001uf note 1: ce0, oe1, clk_sel, pll_by pass, s_a0 and s_a1 are digit al control inputs. if external pull-up/ down needed, see "logic input pin examples" shown at le ft. please note t hat oe0 and oe1 are internally pulled up so no external pull-ups are required to enable them. r5 100 nclk0 clk0 r9 125 r14 84 r1 0 12 5 clk1 r15 84 rs1 470k cp 1 0.001uf cs1 1uf lf0 lf1 2 -p o le lo o p fi lte r - ( op t io n a l ) 3-pole loop filter s_ a0 pl l _b y pas s co n f ig s_ a1 clk_sel clk_active clkbad holdover oe0 xtalbad clk1bad (note 1) oe1 note s (note 2) (note 1) note 3: ot her configurations are supported. please contact idt for details. note 2: clk_sel, pll_bypass and config are internally pulled down. no ext ernal com pononents required to select default condit ion. lvds input e xam pl e (see note 3) vd d c4 0.1uf c5 0.1uf c6 0.1uf c7 0.1uf r11 4.7k r12 4.7k sd ata sc l k c14 10uf c13 0.1uf 3. 3 v c15 0.1uf r1 43 zo = 50 ohm 3.3v lv cmos/lv ttl r4 43 zo = 50 ohm 3.3v lv cmos/lv ttl pecl input e xam pl e (see note 3) nclk1 fb3 bl m18 b b221 s n 1 fox 325bs crystal xta l_o u t x2 1 3 2 4 16mhz to 40 mhz (12pf) xtal _ i n
ics840n202cki revision a november 1, 2013 27 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator power considerations this section provides information on power dissipati on and junction temperature for the ICS840N202I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS840N202I is the sum of the core power plus the power dissipated into the load. the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd + i ddo ) + i dda = 3.465v * 320ma = 1108.8mw lvcmos output power dissipation ? output impedance r out power dissipation due to loading 50 ? to v ddo /2 output current i out = v ddo_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 15 ? )] = 26.65ma ? power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 15 ? * (26.65ma) 2 = 10.65mw per output ? total power (r out ) = 10.65mw * 2 = 21.3mw total power dissipation ? total power = power (core) + total power (r out ) = 1108.8mw + 21.3mw = 1130.1mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 32.4c/w per table 9 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.130w * 32.4c/w = 121.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 9. thermal resistance ? ja for 40 lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 32.4c/w 25.7c/w 23.4c/w
ics840n202cki revision a november 1, 2013 28 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator reliability information table 10. ? ja vs. air flow table for a 40 lead vfqfn transistor count the transistor count for ICS840N202I is: 50,462 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 32.4c/w 25.7c/w 23.4c/w
ics840n202cki revision a november 1, 2013 29 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator package outline and package dimensions package outline - k suffix for 40 lead vfqfn table 11. package dimensions reference document: jede c publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 11. to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil s ingu l a tion or sawn s ingu l a tion n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there a re 2 methods of indica ting pin 1 corner a t the back of the vfqfn pa cka ge: 1. type a: cha mfer on the pa ddle (nea r pin 1) 2. type c: mouse b ite on the pa ddle (nea r pin 1) jedec variation: vjjd-2/-5 all dimensions in millimeters symbol minimum maximum n 40 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.30 n d & n e 10 d & e 6.00 basic d2 & e2 4.55 4.75 e 0.50 basic l 0.30 0.50
ics840n202cki revision a november 1, 2013 30 ?2013 integrated device technology, inc. ICS840N202I data sheet femtoclock? ng universal frequency translator ordering information table 12. ordering information note: for the specific -ddd order codes, refer to femtoclock ng universal frequency tran slator ordering product information document. part/order number marking package shipping packaging temperature 840n202cki-dddlf ics0202ciddd ?lead-free? 40 lead vfqfn tray -40 ? c to +85 ?c 840n202cki-dddlft ics0202ciddd ?lead-free? 40 lead vfqfn tape & reel -40 ? c to +85 ?c
ICS840N202I data sheet femtoclock? ng universal frequency translator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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